This invention relates to semiconductor technology and, in particular, to trenched structures for isolating active regions in semiconductor devices.
For an electronic device created from a semiconductor body to operate efficiently, active regions in the semiconductor body normally have to be laterally electrically isolated from another along a surface of the body. A variety of techniques have been investigated for laterally isolating active semiconductor regions. One highly promising isolation technique is shallow trench isolation (xe2x80x9cSTIxe2x80x9d) in which a shallow patterned trench filled with dielectric material is provided along a surface of a semiconductor body. A portion of the trench laterally surrounds each active semiconductor region. STI is advantageous because it permits the lateral device density, i.e., the density of transistors and other electronic elements present along the surface of the trench-isolated semiconductor body, to be quite high.
FIGS. 1a-1e illustrate how STI is conventionally provided in a monocrystalline silicon semiconductor substrate 20. A thin silicon-oxide layer 22 is provided along the upper surface of substrate 20. See FIG. 1a. A considerably thicker silicon-nitride layer 24 is deposited on oxide layer 22.
Referring to FIG. 1b, a photoresist mask 26 is formed on nitride layer 24. The exposed material of nitride 24 and the underlying material of oxide 22 are removed as indicated in FIG. 1b. Items 22A and 24A in FIG. 1b respectively indicate the remainders of oxide 22 and nitride 24. The exposed silicon is etched to form a shallow patterned trench 28 in substrate 20. A dielectric layer 30, normally consisting of oxide, is deposited on top of the structure and into trench 28 to an average thickness sufficient to fill trench 28. See FIG. 1c. The upper surface of dielectric 30 has depressions, whose depth varies from point to point, above trench 28.
A chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d) technique is utilized to remove the portions of dielectric layer 30 situated above nitride 24A. A portion of the thickness of nitride 24A is also removed during the CMP operation. FIG. 1d illustrates how the structure ideally appears after the CMP operation. Dielectric material 30A, the remainder of dielectric 30, fills trench 28. Item 24B in FIG. 1d is the thinned remainder of nitride 24A.
Remaining nitride 24B is removed to produce the ideal trench-isolated structure shown in FIG. 1e. Items 32 in FIG. 1e indicate trench-isolated active regions of substrate 20. Inasmuch as the sidewalls of trench 28 are nearly vertical, the device density can be very high. Also, the upper surface of the trench-isolated structure is relatively flat, thereby facilitating subsequent manufacturing operations.
In actual practice, it is difficult to achieve the ideal trench-isolated structure shown in FIG. 1e. Various deviations from ideality arise, largely due to the inability to compensate, during the CMP operation, for variations in the lateral width of trench 28 and for variations in the spacing between portions of trench 28. These variations arise from the pattern of the circuitry being created and are referred to here as pattern density variations. FIGS. 2a and 2b illustrate one of the conventional difficulties caused by pattern density variations, while FIGS. 3a and 3b illustrate another of the conventional difficulties caused by pattern density variations.
FIG. 2a depicts how part of the trench-isolated structure often actually appears at the stage of FIG. 1d directly after the CMP operation. FIG. 2b depicts how that part of the trench-isolated structure often actually appears at the stage of FIG. 1e after the removal of nitride 24B. Item 34 in FIGS. 2a and 2b indicates a region where dielectric-filled trench 28 is relatively wide in both lateral directions and, consequently, where the depression in dielectric layer 30 is relatively deep at the stage of FIG. 1c. Although the CMP operation serves to provide trench dielectric region 30A with a moderately flat upper surface, the CMP operation often cannot fully compensate for the greater depression depth at region 34. Consequently, trench dielectric region 30A has a depression at region 34. This phenomenon, commonly termed xe2x80x9cdishingxe2x80x9d, is disadvantageous because it degrades the upper surface planarity.
FIGS. 3a and 3b similarly respectively depict how part of the trench-isolated structure often actually appears at the stages of FIGS. 1d and 1e. Item 36 in FIGS. 3a and 3b indicates a region where portions of trench 28 are quite close to each other and are relatively wide in the lateral direction perpendicular to the sidewalls of region 36. Due to this geometry at region 36, the portion of nitride 24A at region 36, and the underlying portion of oxide 22A, are often removed during the CMP operation. The underlying silicon becomes exposed during the CMP operation and is often damaged, leading to performance loss.
Various measures have been utilized to overcome the dishing and premature nitride removal problems that result from pattern density variations. These measures include (a) providing dummy active regions in areas where trench 28 would otherwise be quite wide in both lateral directions, (b) performing additional etching to remove certain parts of dielectric 30 before performing the CMP operation, and (c) implementing the CMP operation with a slurry that has high oxide-to-nitride etch selectivity. See (a) Grillaert et al, xe2x80x9cA novel approach for the elimination of the pattern density dependence of CMP for shallow trench isolation,xe2x80x9d Tech. Dig., 1998 CMP-MIC Conf., Feb. 19-20, 1998, pages 313-318, (b) Withers et al, xe2x80x9cA Wide Margin CMP and Clean Process for Shallow Trench Isolation Applications,xe2x80x9d Tech. Dig., 1998 CMP-MIC Conf., Feb. 19-20, 1998, pages 319-327, (c) Hosali et al, xe2x80x9cPlanarization Process and Consumable Development for Shallow Trench Isolation,xe2x80x9d Tech. Dig., 1997 CMP-MIC Conf., Feb. 13-14, 1997, pages 52-57, (d) Mills et al, xe2x80x9cRaising Oxide:Nitride Selectivity to Aid in the CMP of Shallow Trench Isolation Type Applications,xe2x80x9d Tech. Dig., 1997 CMP-MIC Conf., Feb. 13-14, 1997, pages 179-185, and (e) Detzel et al, xe2x80x9cComparison of the Performance of Slurries for STI Processing,xe2x80x9d Tech. Dig., 1997 CMP-MIC Conf., Feb. 13-14, 1997, pages 202-206.
The preceding measures achieve varying degrees of success in compensating for pattern density variations and overcoming problems such as dishing and premature nitride removal. Unfortunately, these measures increase the process complexity considerably. Some of them require special computer algorithms for creating masks used in additional lithographic steps. The cost of STI is increased substantially. It is desirable to implement an STI process in a simple, low-cost manner in which the sensitivity to pattern density variations very small.
The present invention furnishes such an implementation of the shallow trench isolation process. In the invention, a pre-smoothening technique is employed to overcome difficulties that might otherwise arise due to pattern density variations. Use of the present pre-smoothening technique results in a fully adequate trench-isolated structure without significantly increasing process complexity, and thus without significantly increasing fabrication costs.
More particularly, in accordance with the invention, a patterned trench is formed in a semiconductor body along its upper surface. The sidewalls of the trench are normally roughly vertical. A dielectric layer having a rough upper surface is provided in the trench and over the semiconductor material outside the trench.
The dielectric layer is covered with a smoothening layer whose upper surface is smoother than the rough upper surface of the dielectric layer. The smoothening layer is typically formed with material, such as spinon glass or borophosphosilicate glass, that can be readily provided with a largely planar upper surface. For example, after furnishing suitable smoothening material over the dielectric layer, the semiconductor body and overlying material can be spun to create the smoothening layer from the smoothening material. The spinning operation can be initiated before the smoothening material is provided over the dielectric layer. Also, the smoothening material can be heated to cause it to flow and thereby smoothen its upper surface.
Starting largely from the upper surface of the smoothening layer and going downward, the smoothening layer is progressively removed. As the smoothening layer is being removed, material of the dielectric layer becomes progressively exposed and is likewise removed. The removal operation is normally continued until largely all of the material of the dielectric layer to the sides of the trench is removed. At the end of the removal operation, part of the dielectric layer remains and has a smoother upper surface than the initial rough surface of the dielectric layer. In effect, the relatively smooth upper surface of the smoothening layer is transferred to the remainder of the dielectric layer.
Chemical-mechanical polishing is typically employed in removing the smoothening layer and the resulting exposed material of the dielectric layer. The removal operation is normally performed in such a way that the rate dzS/dt of removing the material of the smoothening layer is moderately close to the rate dzD/dt of removing material of the dielectric layer. The ratio RS/D of the smoothening-material removal rate dzS/dt to the dielectric-material removal rate dzD/dt normally ranges from 0.2 to 5, preferably from 0.5 to 2. By performing the removal operation in this manner, the upper surface of the remainder of the dielectric layer is normally quite flat. Dishing is largely avoided.
Returning to the process stage at which the trench is created, the trench is normally formed by etching the semiconductor body through a opening in a mask provided over the semiconductor body. The dielectric layer is then provided over a specified region of the mask. The specified mask region is preferably formed primarily with silicon nitride.
During the removal step, the material of the smoothening and dielectric layers overlying the specified mask region is removed. Part of the specified mask region is also normally removed during the removal step. However, due to the use of the smoothening layer, the entire thickness of the specified mask region is normally not removed at any location during the removal step. In particular, complete removal of the material of the specified mask region is avoided at locations where portions of the trench are close to one another and are relatively wide in the lateral direction perpendicular to the sidewalls of the intervening portion of the semiconductor body. The invention thereby overcomes the premature silicon-nitride removal difficulty and attendant damage to the underlying semiconductor material that commonly occurs in the prior art.
The STI process of the invention is relatively simple. Very little, essentially no, sensitivity to pattern density variations arises in the present STI process. There is no need for highly selective, and potentially very expensive, etchant slurries during chemical-mechanical polishing. Nor is there any need to provide dummy active regions which compensate for pattern density variations but which complicate the device layout design, increase the mask cost, and limit the design flexibity. In short, the present STI process yields an excellent trench-isolated structure at a comparatively low fabrication cost. The invention thus provides a large advance over the prior art.